1. Field of the Invention
The present invention relates to an error pulse width expanding circuit and more particularly to a circuit for expanding the width of a plurality of error pulse detected sequentially within one frame during digital transmission.
2. Description of the Prior Art
In the digital transmission, a parity check system has been known as a method for detecting an error rate of transmission path. In this parity check system, a number of logic value "1" in the transmitting data is counted, for example, in the transmitting side. In the case where a result of the predetermined one frame is even, "0" is inserted to the determined position of the next frame and is then transmitted. On the other hand, in the case the result is odd, "1" is inserted and transmitted. In the receiving side, a value counted from the receiving data is compared, in the same manner as the transmitting side, with the bit (parity bit) inserted in the transmitting side. If these values are different, these data are detected and processed as the error pulses in an error counter.
This error pulse continues for the period as long as one frame and is equal to the one bit length of the main signal. Therefore, it has a very short pulse width. Accordingly, an error counting circuit, which sufficiently counts the error pulse in low speed operation by expanding the pulse width of the error pulse and realizes improvement in reliability of error detection and simplification of circuit structure, has been proposed in the Japanese unexamined patent publication Tokukai-Sho 64-46339. However, this conventional circuit is provided for expanding pulse width of error pulses detected bit by bit in each frame. Therefore, this circuit provides a problem that it cannot be applied to the system where a plurality of parity bits (error pulse) exist within the one frame such as the frame format of the STS-12 signal which is employed, for example, in the SONET (Synchronous Optical NETwork) as the broadband ISDN.